1) Field of the Invention
The present invention relates to an image processing system, and in particular to an image processing system which performs processing for encoding and decoding image signals.
2) Description of the Related Art
In recent years, in the fields of DVD (Digital Versatile Disc) and digital TV broadcasting, the MPEG (Moving Picture Experts Group) techniques have been widely used in order to record and transmit massive amounts of image data with high quality. In the MPEG image processing, an image signal is divided into a plurality of portions, and each portion is written in and read out from a memory, and encoded or decoded.
FIG. 14 is a diagram illustrating a conventional image processing system. As illustrated in this diagram, the conventional image processing system 50 comprises an image processing unit 51 and memories 52 and 53. The image processing unit 51 is connected to the memories 52 and 53 through memory buses b1 and b2.
The image processing unit 51 performs processing for encoding and decoding image signals which are inputted into the image processing unit 51. The memories 52 and 53 store the image signals inputted into the image processing system 50 and image signals which have been processed by the image processing unit 51. At this time, the memory 52 stores image signals corresponding to the upper area (upper half) of the screen, control information related to encoding and decoding of the image signals corresponding to the upper area, and the like, and the memory 53 stores image signals corresponding to the lower area (lower half) of the screen, control information related to encoding and decoding of the image signals corresponding to the lower area, and the like.
In addition, the memories 52 and 53 have working areas for storing an OS (operating system) and data related to control of the entire system, as well as areas for storing data related to the encoding and decoding.
FIG. 15 is a diagram indicating data flow rates through the memory buses b1 and b2. In FIG. 15, the graph Ga indicates the data flow rate through the memory bus b1, and the graph Gb indicates the data flow rate through the memory bus b2. In the graphs Ga and Gb, the abscissa corresponds to time progression, and the ordinate corresponds to the data flow rate.
When image signals corresponding to the upper area of the screen are processed, the data flow rate through the memory bus b1 increases since the image signals corresponding to the upper area of the screen are stored in the memory 52. On the other hand, when image signals corresponding to the lower area of the screen are processed, the data flow rate through the memory bus b2 increases since the image signals corresponding to the lower area of the screen are stored in the memory 53.
Further, since a CPU (central processing unit) is also connected to the memory buses b1 and b2, and uses some areas of the memories 52 and 53, data stored in the working areas flow through the memory buses b1 and b2 when the CPU accesses the working areas, regardless of the processing of the image signals corresponding to the upper and lower areas of the screen.
On the other hand, in the case where data are divided into a plurality of channels and encoded, image deterioration can occur at the boundaries between data in different channels. Conventionally, a technique for preventing such image deterioration at the boundaries between data in different channels has been proposed. See, for example, Japanese Unexamined Patent Publication No. 05-183891, Paragraphs. [0013] to [0023] and FIG. 1.